Nonvolatile semiconductor  memory and method for controlling the same

ABSTRACT

A nonvolatile semiconductor memory includes a memory cell array, a flag information storage that stores a write flag indicating success/failure of writing in association with each address of a plurality of data segments contained in the data block, an internal address storage that selects the address where the writing has failed, a write circuit that performs data writing, a comparator that performs verify operation to verify success/failure of the data writing, and a sequence controller that updates a write flag according to the result of the verify operation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a nonvolatile semiconductormemory and a method for controlling the same and more particularly to anonvolatile semiconductor memory that performs writing and erasing inunits of a plurality of memory cells (data) and a method for controllingthe same.

2. Description of Related Art

Electrically Erasable and Programmable ROM (EEPROM) is widely known as anonvolatile memory which is electrically erasable and programmable. Aflash memory, which is one type of EEPROM and erasable in units ofblocks, has a significantly increasing memory capacity and gainsattention as a memory to substitute for a disc or the like.

In the flash memory, a memory cell is composed of a transistor having afloating gate and a control gate. Data is recorded by electricallywriting data on the memory cell transistor. Data is erased byelectrically erasing data on the memory cell transistor.

In the electrical writing on the memory cell transistor, a high voltagefor writing is applied to the control gate and the drain of the memorycell transistor. Electrons are thereby injected to the floating gate,setting a threshold of the memory cell transistor to be higher.

For example, as shown in FIG. 17, a flash memory which switches thethreshold of the memory cell transistor between two levels by one-timeelectrical writing and stores the data of “0” and “1” in one memory celltransistor is called a binary flash memory. As shown in FIG. 18, a flashmemory which switches the threshold of the memory cell transistor amonga plurality of levels by a plurality of times of electrical writing andstores a plurality of data segments such as the data of “0”, “1”, “2”and “3” in one memory cell transistor is called a multivalued flashmemory. Though the use of the multivalued flash memory allows anincrease in memory capacity, it increases the number of writing timesaccordingly. For instance, the flash memory of FIG. 18 requires threetimes of writing in order to change the state of the memory celltransistor from the state storing the data “3” to the state storing thedata “0”.

Further, after writing data to the memory cell transistor, the readoperation called “verify” is performed in order to verify that thethreshold of the memory cell transistor reaches a target value. Thus,the data write operation is implemented by automatically repeating theelectrical writing and the verify operation (automatic writing) and itis necessary to provide a device for controlling the repetition forevery target memory cell. Similarly in the data erase operation, it isnecessary to provide an automatic erase control device whichautomatically repeats the electrical erasing and the verify operationfor every target memory cell.

In this way, recording and erasing of data on the flash memory requiressequence control such as automatic writing or automatic erasing.Reduction of the processing time by using a suitable flow is one factorto determine the commercial value.

FIG. 19 shows the structure of a nonvolatile semiconductor memory of arelated art. As shown in FIG. 19, the nonvolatile semiconductor memoryincludes a buffer 901 that latches an external address or external datasupplied from outside, a sequence controller 904 that controls a writesequence, a memory cell array 907 that has memory cells arranged inarray, a read circuit 905 that reads data from the memory cell array907, a write circuit 906 that writes data to the memory cell array 907,and a comparator 909 that compares the data read from the memory cellarray 907 with external data.

The flowchart of FIG. 20 shows an automatic write operation in thenonvolatile semiconductor memory of a related art. The automatic writeoperation is implemented by the control of the sequence controller 904.

Initially, one external address and one external data to be written areinput as a command through an external bus or the like and stored in thebuffer 901 (S901). Then, the read circuit 905 performs the readoperation on the memory cell of the memory cell array 907 which isspecified by the external address under the control of the sequencecontroller 904 (S902). Then, the comparator 909 determines whether theread data corresponds to the input external data (S903). The process ofthe steps S902 and S903 is the verify operation.

If it is determined in the step S903 that the data correspond to eachother, the sequence controller 904 terminates the automatic writeoperation. If, on the other hand, it is determined in the step S903 thatthe data does not correspond, the write circuit 906 performs the writeoperation of the external data into the memory cell of the memory cellarray 907 which is specified by the external address under the controlof the sequence controller 904 (S904). After that, the process furtherperforms the verify operation (S902 and S903), and repeats the writeoperation and the verify operation until the data of the memory cellcorresponds to the external data.

Japanese Unexamined Patent Application Publications Nos. 2002-366420 andH6-195989 include the disclosure concerning a nonvolatile semiconductormemory. The technique disclosed therein sets a flag that indicates thecompletion of erasing for each block or sector.

However, since the conventional nonvolatile semiconductor memory inputsa command (one address and one data) from the outside with respect toeach writing or erasing on one address, it has a disadvantage of a lowprocessing efficiency of writing or erasing to take a long time for thewrite and erase operation.

FIG. 21 shows the operation of writing a plurality of data segments inchronological order in the conventional nonvolatile semiconductormemory. This is the case where the verify succeeds in one-time writing.

In order to write first data, the operation first inputs one address andone data in T101. Then, it performs the verify before writing(pre-verify) in T102, writes one data in the memory cell of one addressin T103, and then performs the verify after writing (post-verify) inT104. The writing of the first data thereby completes. Then, in order towrite second data, the operation further inputs one address and one dataand writes the data in the same manner as above. The operation of T101to T104 is repeated for the number of data segments to be written.

Therefore, even in the case where it is possible to identify otheraddresses with one address such as when writing a large amount of datato successive addresses, it is necessary to input an address and dataeach time for every address of data to be written, thus forcing toperform the input operation in vain.

External commands are input from CPU or the like through a bus. With therecent increase in processing speed of CPU and bus, transfer speed andcapacity, a large amount of successive data segments are input in manycases. Thus, the useless processing for each address causes significantdeterioration in the overall efficiency and processing time of the datawrite or erase operation.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided anonvolatile semiconductor memory that has a sector containing aplurality of memory cells as a minimum unit of data erase operation,which includes an input section for batch-inputting data segments to bewritten to a plurality of addresses in the sector, a flag storage forstoring states of the memory cells respectively corresponding to theplurality of addresses, and an address setting circuit for determiningan address to be selected according to information in the flag storage.

The nonvolatile semiconductor memory performs batch input of a pluralityof addresses and data segments, thereby eliminating the need forinputting a command for each of a plurality of addresses. It is therebypossible to improve the write/erase operation efficiency and reduce theprocessing time. Further, by setting a flag for each address, it ispossible to perform the data write/erase operation on a memory cell moreefficiency compared with the case of setting a flag for each sector.

According to another aspect of the present invention, there is provideda nonvolatile semiconductor memory that performs write/erase operationin units of data block containing a plurality of data segments, whichincludes a memory cell array including a plurality of nonvolatile memorycells, a flag storage for storing a flag provided for each address andindicating success/failure of the write/erase operation in associationwith each address of the plurality of data segments contained in thedata block, an address selector for selecting the address where thewrite/erase operation has failed according to the stored flag, awriting/erasing section for performing the write/erase operation of thedata segments on the nonvolatile memory cell located in the selectedaddress, a verify section for performing verify operation to verifysuccess/failure of the data write/erase operation on the nonvolatilememory cell located in the selected address, and a flag update sectionfor updating the flag according to a result of the verify operation.

The nonvolatile semiconductor memory performs writing and erasing inunits of a plurality of data segments, thereby eliminating the need forinputting a command for each of a plurality of addresses. It is therebypossible to improve the writing and erasing processing efficiency andreduce the processing time. Further, by setting a flag for each addresswhere data is to be written or erased, it is possible to perform writingand erasing more efficiency compared with the case of setting a flag fora unit of a plurality of data segments.

The present invention provides a nonvolatile semiconductor memorycapable of improving writing and erasing processing efficiency andreducing a writing and erasing processing time and a method forcontrolling the same.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the presentinvention will be more apparent from the following description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing the structure of a nonvolatilesemiconductor memory according to an embodiment of the presentinvention;

FIG. 2 is a view to describe the flow of write operation of anonvolatile semiconductor memory according to an embodiment of thepresent invention;

FIG. 3 is a flowchart showing write operation of a nonvolatilesemiconductor memory according to an embodiment of the presentinvention;

FIGS. 4A to 4C are views showing an example of a write flag used in anonvolatile semiconductor memory according to an embodiment of thepresent invention;

FIGS. 5A and 5B are flowcharts showing write operation of a nonvolatilesemiconductor memory according to an embodiment of the presentinvention;

FIG. 6 is a block diagram showing the structure of a nonvolatilesemiconductor memory according to an embodiment of the presentinvention;

FIG. 7 is a flowchart showing write operation of a nonvolatilesemiconductor memory according to an embodiment of the presentinvention;

FIGS. 8A and 8B are flowcharts showing write operation of a nonvolatilesemiconductor memory according to an embodiment of the presentinvention;

FIG. 9 is a block diagram showing the structure of a next addresscalculator of a nonvolatile semiconductor memory according to anembodiment of the present invention;

FIG. 10 is a flowchart showing address selection operation of anonvolatile semiconductor memory according to an embodiment of thepresent invention;

FIG. 11 is a flowchart showing a next address calculation operation of anonvolatile semiconductor memory according to an embodiment of thepresent invention;

FIG. 12 is a flowchart showing a last address calculation operation of anonvolatile semiconductor memory according to an embodiment of thepresent invention;

FIG. 13 is a circuit diagram showing the structure of a next executionaddress calculator of a nonvolatile semiconductor memory according to anembodiment of the present invention;

FIG. 14 is a circuit diagram showing the structure of a last addresscalculator of a nonvolatile semiconductor memory according to anembodiment of the present invention;

FIG. 15 is a graph showing a calculation example of a write operationtime according to a first and a second embodiment of the presentinvention;

FIG. 16 is a block diagram showing the structure of a next addresscalculator of a nonvolatile semiconductor memory according to anembodiment of the present invention;

FIG. 17 is a graph showing a change in a threshold of a memory cell in atypical binary flash memory;

FIG. 18 is a graph showing a change in a threshold of a memory cell in atypical multivalued flash memory;

FIG. 19 is a block diagram showing the structure of a nonvolatilesemiconductor memory of a related art;

FIG. 20 is a flowchart showing write operation of a nonvolatilesemiconductor memory of a related art; and

FIG. 21 is a view to describe the flow of write operation of anonvolatile semiconductor memory of a related art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be now described herein with reference toillustrative embodiments. Those skilled in the art will recognize thatmany alternative embodiments can be accomplished using the teachings ofthe present invention and that the invention is not limited to theembodiments illustrated for explanatory purposed.

First Embodiment

A nonvolatile semiconductor memory according to a first embodiment ofthe present invention is described hereinafter. The nonvolatilesemiconductor memory of this embodiment allows batch input of datasegments with successive addresses. Further, it sets a flag indicatingcompletion of writing for each address so that a counter sequentiallyselects and processes each flag.

Referring first to FIG. 1, the structure of the nonvolatilesemiconductor memory according to this embodiment is describedhereinafter. The nonvolatile semiconductor memory is a semiconductordevice including a flash memory and a controller, for example, andtemporarily stores a sequence of data to be written in a buffer and thensequentially writes the data.

As shown in FIG. 1, the nonvolatile semiconductor memory includes abuffer 1, an internal address counter 2, a flag information storage 3, asequence controller 4, a read circuit 5, a write circuit 6, a memorycell array 7 and a comparator 9.

The buffer 1 temporarily stores an external address and external datasupplied through an external bus or the like. The external address andexternal data are the address and data to be written. Particularly, inthis embodiment, the external data is a data block containing aplurality of successive data segments and the external address is a topaddress of the data block of the external data. Thus, the buffer 1serves as an input section that inputs at a time the data segments to bewritten to a plurality of addresses in a sector.

The internal address counter 2 selects an internal address where data tobe written or read from the memory cell array 7 according to a countervalue. The internal address counter 2 is an address setting circuit(address selector) 20 that determines an address to be supplied to thememory array 7 according to a write flag stored in the flag informationstorage 3. For example, the counter value may be an internal address oran offset from the top address. The internal address is an address tospecify the memory cell in the memory cell array 7, and it may be thesame as the external address supplied from the outside or an addressconverted from the external address for writing to the memory cell array7. One of the external addresses always corresponds to one of theinternal addresses.

The flag information storage (flag storage) 3 stores a write flag foreach address of external data (each internal address) stored in thebuffer 1. The write flag is stored in association with the address ofthe memory cell (data) in the memory cell array 7 and it indicates thestate of each memory cell (data). The write flag indicates the successor failure of writing of each data, that is, indicates if writing hascompleted for each data. If the write flag is set, it indicates thewriting failed, which means it is a target for writing. If, on the otherhand, the write flag is not set or reset, it indicates the writingsucceeded, which means it is not a target for writing.

In the memory cell array 7, a plurality of memory cells are arranged inarray. The memory cells are nonvolatile memory cells such as a flashmemory. For example, the memory cell array 7 may be divided into severalsectors each having a plurality of memory cells and being a minimum unitfor erasing. The read circuit 5 reads the data from the memory cell inthe memory cell array 7 which has the internal address selected by theinternal address counter 2. The write circuit 6 writes the external datastored in the buffer 1 to the memory cell in the memory cell array 7which has the internal address selected by the internal address counter2. Thus, the write circuit 6 is a writing or erasing section 22 thatperforms data write or read operation on the memory cell. The comparator9 compares the data read from the memory cell array 7 by the readcircuit 5 with the external data stored in the buffer 1. Thus, thecomparator 9 is a verify section 23 that performs verify operation fordetermining if the data write or erase operation is succeeded or failed.

The sequence controller 4 controls the operation of each component andimplements a sequence of automatic write operation. The sequencecontroller 4 also serves as a flag updating section 21 for updating awrite flag according to the verify result of the comparator 9. Forexample, the sequence controller 4 operates the read circuit 5 or thewrite circuit 6 according to the write flag in the flag informationstorage 3, updates the write flag in the flag information storage 3according to the comparison result in the comparator 9 and updates thecounter value of the internal address counter 2.

The sequence controller 4 includes a command decoder. The commanddecoder recognizes a command for automatic input operation, enablingcontinuous inputs of write addresses and write data.

Referring next to FIG. 2, the automatic write operation of thenonvolatile semiconductor memory according to this embodiment isdescribed schematically. FIG. 2 shows the flow of data write operationin chronological order. It shows the case where the verify succeeds inone-time writing.

In T1, the operation inputs an address and data at a time after decodingthe command indicating the automatic write operation. Thus, a pluralityof data segments and a top address are input and stored in the buffer 1.At the same time, the operation sets a write flag corresponding to eachaddress to the flag information storage 3.

In T2, the operation checks the write flag in the flag informationstorage 3 and performs the verify before writing (pre-verify) accordingto the flag and then, in accordance with the verify result, updates theflag. The verify operation is repeated for the number of addresses wherethe write flag is set.

In T3, the operation checks the write flag in the flag informationstorage 3 and writes the data in the buffer 1 into the memory cell ofthe memory cell array 7 according to the flag. The write operation isrepeated for the number of addresses where the write flag is set.

In T4, the operation checks the write flag in the flag informationstorage 3 and performs the verify after writing (post-verify) accordingto the flag and then, in accordance with the verify result, updates theflag. The verify operation is repeated for the number of addresses wherethe write flag is set. Further, if the address where writing has beenfailed, which is the address where the write flag is set, remains afterthe verify, the write operation in T3 and the verify operation in T4 arerepeated until the writing is all succeeded.

In this way, this embodiment allows batch input of a plurality of datasegments and addresses, thereby eliminating the need for inputting acommand (address and data) for each data, which has been required in therelated art shown in FIG. 21. It is thereby possible to reduce theprocessing time for write operation.

Referring then to the flowchart of FIG. 3, the automatic write operationof the nonvolatile semiconductor memory according to this embodiment isdescribed in further detail herein. The automatic write operation isimplemented by the control of the sequence controller 4.

Initially, the external addresses and external data segments to bewritten are input to the buffer 1 at a time as a command from theoutside after decoding the command of the automatic writeoperation(S201). As described above, a plurality of successive datasegments and their top addresses are input thereby.

Then, the input external data is stored in a corresponding address ofthe buffer 1, and the write flag associated with the address (internaladdress) where the data is to be written is stored in the flaginformation storage 3 (S202). Since writing has not been performedimmediately after the input of the external address and external data,which is at the time of first verify, the write flags in the flaginformation storage 3 are all set.

After that, the sequence controller 4 resets the counter value of theinternal address counter 2 (S203). By setting the counter value to “0”,the internal address counter 2 selects the top address of the memorycell.

Then, the sequence controller 4 determines whether the write flag is setfor the internal address selected by the internal address counter 2(S204). Specifically, it refers to the write flag of the selectedinternal address which is stored in the flag information storage 3 anddetermines whether the writing has succeeded on this internal address.

If it is determined in the step S204 that the write flag is set, whichmeans that the selected address is a target for writing, the sequencecontroller 4 controls the read circuit 5 so as to read the data from thememory cell in the memory cell array 7 which has the internal addressselected by the internal address counter 2 (S205).

Then, the comparator 9 determines whether the data read by the readcircuit 5 matches with the data in the buffer 1 (S206). If thecomparator 9 determines in the step S206 that the data matches, it meansthe verify has succeeded (writing has succeeded) and therefore thesequence controller 4 updates to clear the write flag of thecorresponding internal address in the flag information storage 3 (S207).If, on the other and, the comparator 9 determines in the step S206 thatthe data does not match, it means the verify has failed (writing hasfailed) and therefore the sequence controller 4 does not update thewrite flag of the corresponding internal address in the flag informationstorage 3 so that it remains set.

The process of S205 and S206 is the verify operation for checking if thewriting has succeeded. If it is determined in the step S204 that thewrite flag is not set, the writing has already succeeded and thus theprocess does not performs the verify nor the update of the flag (S205 toS207).

Then, the sequence controller 4 determines whether the internal addressselected by the internal address counter 2 is a last address or not(S208). Specifically, it determines whether the internal addressselected according to the counter value reaches the final address of theflag information storage 3. For example, the sequence controller 4 maydetermine that it is the last address when the internal address counter2 overflows. In this embodiment, the last address is not the finaladdress of the data to be written but the final address of the flaginformation storage 3, which is always a fixed address.

If the sequence controller 4 determines in the step S208 that theinternal address selected by the internal address counter 2 is not thelast address, the sequence controller 4 increments the counter value ofthe internal address counter 2 (S209). After that, the sequencecontroller 4 checks the write flag, performs the verify and updates thewrite flag for the internal address selected by the incremented countervalue of the internal address counter 2 (S204 to S207). This is repeateduntil the last address is reached.

If, on the other hand, the sequence controller 4 determines in the stepS208 that the internal address is the last address, it determineswhether the writing has completed for all the data segments (S210). Ifthe all the write flags in the flag information storage 3 are cleared(reset), it means that a sequence of buffer writing has completed. If atleast one write flag in the flag information storage 3 is set, it meansthat the writing has not completed. If the sequence controller 4determines in the step S210 that the writing has all completed, itterminates the automatic write operation.

If, on the other hand, the sequence controller 4 determines in the stepS210 that the writing has not all completed, the sequence controller 4resets the counter value of the internal address counter 2 just like inthe step S203 (S211). Then, like S204, the sequence controller 4determines whether the write flag is set for the internal addressselected by the internal address counter 2 (S212).

If the sequence controller 4 determines in the step S212 that the flagis set, it means that the selected address is a target for writing. Inthis case, the sequence controller 4 controls the write circuit 6 so asto electrically write the corresponding external data in the buffer 1into the memory cell in the memory cell array 7 which has the internaladdress selected by the internal address counter 2 (S213). If, on theother hand, the sequence controller 4 determines in the step S212 thatthe flag is not set, it means that the writing has succeeded. In thiscase, the sequence controller 4 does not perform writing to the memorycell.

After that, the sequence controller 4 determines whether the internaladdress selected by the internal address counter 2 is the last addressor not just like in S208 (S214).

If the sequence controller 4 determines in the step S214 that theinternal address selected by the internal address counter 2 is not thelast address, it increments the counter value of the internal addresscounter 2 just like in S209 (S215).

After that, the sequence controller 4 repeats the checking of the writeflag and the writing to the memory cell for the internal addressselected according to the incremented counter value of the internaladdress counter 2 (S212 to S213). This is repeated until the lastaddress is reached.

If, on the other hand, the sequence controller 4 determines in the stepS214 that the internal address selected by the internal address counter2 is the last address, it again resets the counter value of the internaladdress counter 2 (S203) Then, the process after the step S203 isrepeated until the writing of all the data completes.

FIGS. 4A to 4C show the internal addresses and write flags stored in theflag information storage 3.

In the example of FIGS. 4A to 4C, the internal address is 2 bits, thewrite flag is 1 bit, and four data segments with the internal address(00)b to (11)b are written. In this example, a sequence of automaticwrite process completes in three times of verify operation. FIG. 4Ashows the internal addresses and write flags upon completion of thefirst verify. FIG. 4B shows the internal addresses and write flags uponcompletion of the second verify. FIG. 4C shows the internal addressesand write flags upon completion of the third verify.

When an external address and external data is input, the write flag isset for all of the internal address (00)b to (11)b. In the first verify,the data writing to the memory cell is not performed, and therefore allthe write flags are set upon completion of the first verify as shown inFIG. 4A. In this condition, the first writing is performed to the memorycells with the internal addresses (00)b to (11)b. In this example, thefirst writing succeeds in the internal addresses (01)b and (10)b whileit fails in the internal addresses (00)b and (11)b.

Then, in the second verify, the write flag for the internal addresses(01)b and (10)b are reset to “0”. Thus, upon completion of the secondverify, the flags are set only for the internal addresses (00)b and(11)b as shown in FIG. 4B. In this condition, the second writing isperformed to the memory cells with the internal addresses (00)band(11)b. In this example, the second writing succeeds in the internaladdresses (00)b and (11)b.

Then, in the third verify, the write flag for the internal addresses(00)b and (11)b are reset to “0”. Thus, upon completion of the thirdverify, all the flags are cleared as shown in FIG. 4C. The writeoperation on the internal addresses (00)b to (11)b thereby completes.

FIGS. 5A and 5B show the flow of the verify operation in the example ofFIGS. 4A to 4C. FIG. 5A shows the first or the second verify operationin which the internal addresses and the write flags are in the states asshown in FIG. 4A.

Initially, the sequence controller 4 resets the counter value of theinternal address counter 2 and checks the write flag of the internaladdress (00)b which is selected by the counter value “0” (S301). Sincethe write flag of the internal address (00)b is (1)b, the verifyoperation is performed on the memory cell with the internal address(00)b (S302).

Then, the sequence controller 4 increments the counter value of theinternal address counter 2 and checks the write flag of the internaladdress (01)b which is selected by the counter value “1” (S303). Sincethe write flag of the internal address (01)b is (1)b, the verifyoperation is performed on the memory cell with the internal address(01)b (S304).

Further, in the same manner, the sequence controller 4 increments thecounter value of the internal address counter 2, checks the write flagof the internal address (10)b, performs the verify operation, checks thewrite flag of the internal address (11)b, and performs the verifyoperation (S305 to S308). Then, the address selected by the internaladdress counter 2 reaches the last address, which is the internaladdress (11)b in this case, and thereby the first or the second verifyoperation completes. The first write operation is performed in the sameway as described above by sequentially selecting the internal addresses(00)b to (11)b and writing the data to each address.

FIG. 5B shows the third verify operation in which the internal addressesand the write flags are in the states as shown in FIG. 4B.

Initially, the sequence controller 4 resets the counter value of theinternal address counter 2 and checks the write flag of the internaladdress (00)b which is selected by the counter value “0” (S309). Sincethe write flag of the internal address (00)b is (1)b, the verifyoperation is performed on the memory cell with the internal address(00)b (S310).

Then, the sequence controller 4 increments the counter value of theinternal address counter 2 and checks the write flag of the internaladdress (01)b which is selected by the counter value “1” (S311). Sincethe write flag of the internal address (01)b is (0)b, the verifyoperation is not performed.

Further, the sequence controller 4 increments the counter value of theinternal address counter 2 and checks the write flag of the internaladdress (10)b which is selected by the counter value “2” (S312). Sincethe write flag of the internal address (10)b is (0)b, the verifyoperation is not performed.

Furthermore, the sequence controller 4 increments the counter value ofthe internal address counter 2 and checks the write flag of the internaladdress (11)b which is selected by the counter value “3” (S313). Sincethe write flag of the internal address (11)b is (1)b, the verifyoperation is performed on the memory cell with the internal address(11)b (S314). Then, the address selected by the internal address counter2 reaches the last address, which is the internal address (11)b in thiscase, and thereby the third verify operation completes. The second writeoperation is performed in the same way as described above bysequentially selecting the internal addresses (00)b to (11)b and writingthe data to the internal addresses (00)b. and (11)b.

As described in the foregoing, this embodiment inputs a plurality ofdata segments and the addresses of the data segments at a time as acommand supplied from the outside. This eliminates the need forinputting a command for each data segment, thus enabling the efficientwrite operation and thereby reducing a time for the write operation.

Further, by setting a flag for each of the plurality of addresses andperforming the verify or writing according to the flag, it is possibleto perform the verify or write operation on the data as a unit ofwriting, thus enabling more efficient operation.

Second Embodiment

A nonvolatile semiconductor memory according to the second embodiment ofthe present invention is described hereinafter. The nonvolatilesemiconductor memory of this embodiment allows batch input of datasegments with successive addresses. Further, it sets a flag indicatingcompletion of writing for each address and selects a plurality of flagsand process them in parallel at substantially the same time.

In the first embodiment described above, redundant address selectionoperation can occur when implementing the buffer operation, which cancause a decrease in processing speed. As described with reference toFIGS. 5A and 5B, the first embodiment increments the counter value andsearches for an address where a write flag is set always sequentially.Thus, it selects every address once, even a non-target address where awrite flag is not set. A write operation speed can decrease due to theunnecessary address selection which is always performed in the firstembodiment.

The operation of searching for the write flag is performed each time thewrite operation or the read operation is performed. Thus, as theoperation is repeated, a redundant address selection time increasesaccordingly. The number of redundant addresses in the write flag searchoperation increases as the number of write target addresses decreases.Thus, a redundant processing time increases as the number of addressesspecified by the external command decreases with respect to the buffersize.

To overcome this drawback, the second embodiment selects only anecessary address without selecting addresses always sequentially in thesearch operation for a write flag.

Referring then to FIG. 6, the structure of the nonvolatile semiconductormemory according to this embodiment is described hereinafter. In FIG. 6,the same elements as in FIG. 1 are denoted by the same referencenumerals and not described in detail herein. As shown in FIG. 6, thenonvolatile semiconductor memory of this embodiment includes an internaladdress storage 10 instead of the internal address counter 2 and furtherincludes a next address calculator 8. The internal address storage 10and the next address calculator 8 serve as the address setting circuit20.

The internal address storage 10 stores internal addresses set by thesequence controller 4. It selects an address where data is to be writtenor read from the memory cell array 7 according to the set internaladdress. Thus, though the internal address storage 10 has substantiallythe same structure as the internal address counter 2 in the firstembodiment, only the setting of the internal address is performedtherein and the incrementation is not performed by the sequencecontroller 4.

The next address calculator 8 calculates the address to be selectednext, which is referred to hereinafter as the next address, from theinternal addresses presently set to the internal address storage 10.Since the calculated next address is a write target address, theunnecessary address selection operation as in the first embodiment doesnot occur. In the search (select) operation for the first write flag,the sequence controller 4 inputs an initial set flag. The next addresscalculator 8 calculates the next address and further determines whetherthe address is a last address. If the calculated next address a lastaddress, the next address calculator 8 outputs a last address flag tothe sequence controller 4.

The automatic write operation in the nonvolatile semiconductor memoryaccording to this embodiment is described herein. Since the automaticwrite operation is basically the same as that shown in FIG. 2, thedetail of the automatic write operation of this embodiment is describedherein with reference to the flowchart of FIG. 7.

Initially, the external addresses and external data segments to bewritten are input to the buffer 1 at a time as a command from theoutside after decoding the command of the automatic write operation(S401). As is the case with the first embodiment, a plurality ofsuccessive data segments and their top addresses are input thereby.

Then, the input external data is stored in a corresponding address ofthe buffer 1, and the write flag associated with the address (internaladdress) where the data is to be written is stored in the flaginformation storage 3 (S402).

After that, the next address calculator 8 calculates a next addresswhich is an internal address to be selected next and further calculateswhether the calculated internal address is a last address or not (S403).In this calculation, the next address calculator 8 uses the currentinternal address (initial reset state) from the internal address storage10 and the write flag in the flag information storage 3.

Then, the sequence controller 4 sets the next address calculated by thenext address calculator 8 to the internal address storage 10 (S404). Thenext address calculated by the next address calculator 8 is thereby setas the current internal address so that the internal address storage 10selects the newly set internal address.

The sequence controller 4 then controls the read circuit 5 so as to readthe data from the memory cell in the memory cell array 7 which has theinternal address selected by the internal address storage 10 (S405).

After that, the comparator 9 determines whether the data read by theread circuit 5 matches with the data in the buffer 1 (S406). If thecomparator 9 determines in the step S206 that the data matches, it meansthe verify has succeeded (writing has succeeded) and therefore thesequence controller 4 updates to clear the write flag of thecorresponding address in the flag information storage 3 (S407). If, onthe other and, the comparator 9 determines in the step S206 that thedata does not match, it means the verify has failed (writing has failed)and therefore the sequence controller 4 does not update the write flagof the corresponding address in the flag information storage 3 so thatit remains set.

Then, the sequence controller 4 determines whether the internal addressselected by the internal address storage 10 is a last address or not(S408). Since the next address calculator 8 has already determinedwhether the current internal address is a last address or not and set alast address flag, the sequence controller 4 determines if it is a lastaddress according to the last address flag.

If the sequence controller 4 determines in the step S408 that theaddress selected by the internal address storage 10 is not the lastaddress, the next address calculator 8 again calculates the address tobe selected next based on the current internal address, which is theaddress set last time, from the internal address storage 10 and thewrite flag in the flag information storage 3 and further calculateswhether it is a last address or not (S403). Then, the calculated addressis set to the internal address storage 10 (S404). After that, thesequence controller 4 performs the verify and the update of the writeflag in the same manner (S405 to S407) and repeats this process untilthe last address is reached.

If, on the other hand, the sequence controller 4 determines in the stepS408 that the internal address is the last address, it furtherdetermines whether the writing has completed for all the data segments(S409). If the last address flag indicating that it is the last addressis set by the next address calculator 8 and the write flags in the flaginformation storage 3 are all cleared, it means that a sequence ofautomatic write operation completes. If at least one write flag in theflag information storage 3 is set, it means that the writing has notcompleted. If the sequence controller 4 determines in the step S409 thatthe writing has all completed, it terminates the automatic writeoperation.

If, on the other hand, the sequence controller 4 determines in the stepS409 that the writing has not all completed, the next address calculator8 calculates the address to be selected next based on the currentinternal address (reset state) in the internal address storage 10 andthe write flag in the flag information storage 3 and further calculateswhether it is a last address or not just like in S403 (S410).

Then, the sequence controller 4 sets the next address calculated by thenext address calculator 8 to the internal address storage 10 just likein S404 (S411).

The sequence controller 4 then controls the write circuit 6 so as toelectrically write the corresponding external data in the buffer 1 intothe memory cell in the memory cell array 7 which has the addressselected by the internal address storage 10 (S412).

Then, the sequence controller 4 determines whether the address selectedby the internal address storage 10 is a last address or not just like inS408 (S413). If the sequence controller 4 determines in the step S413that the address selected by the internal address storage 10 is not thelast address and when the last address flag indicating a last address isnot set by the next address calculator 8, the next address calculator 8again calculates the address to be selected next based on the currentinternal address, which is the address set last time, in the internaladdress storage 10 and the write flag in the flag information storage 3and further calculates whether it is a last address or not (S410). Then,the calculated address is set to the internal address storage 10 (S411).After that, the sequence controller 4 performs the write operation inthe same manner (S412) and repeats this process until the last addressis reached.

If, on the other hand, the sequence controller 4 determines in the stepS413 that the address selected by the internal address storage 10 is thelast address and when the last address flag indicating a last address isset by the next address calculator 8, the next address calculator 8again calculates the next address (S403). After that, the process afterthe step S403 is repeated until the writing of all the data segmentscompletes.

Referring now to FIGS. 8A and 8B, a specific example of the automaticwrite operation in the nonvolatile semiconductor memory according tothis embodiment is described hereinafter. FIGS. 8A and 8B show eachverify operation in the example of FIGS. 4A to 4C just like FIGS. 5A and5B in the first embodiment.

FIG. 8A shows the first or the second verify operation in which theinternal addresses and the write flags are in the states as shown inFIG. 4A.

Since it is initial condition, the next address calculator 8 checks allthe write flags for the internal addresses (00)b to (11)b at the sametime and calculates a minimum internal address for which the write flagis set (S501). Since the write flag for the internal address (00)b is(1)b, the internal address (00)b is calculated and set to the internaladdress storage 10 so that the internal address (00)b is selected. Then,the verify operation is performed on the memory cell with the internaladdress (00)b (S502).

Then, since the internal address (00)b is selected in the internaladdress storage 10, the next address calculator 8 checks all the writeflags for the internal address larger than (00)b, which is the internaladdresses (01)b to (11)b, at the same time and calculates a minimuminternal address for which the write flag is set (S503). Since the writeflag for the internal address (01)b is (1)b, the internal address (01)bis calculated and set to the internal address storage 10 so that theinternal address (01)b is selected. Then, the verify operation isperformed on the memory cell with the internal address (01)b (S504).

In this way, the process further checks the write flags for the internaladdress (10)b and the internal address (11)b when the internal addressis (01)b (S505) and verifies the memory cell with the internal address(11)b (S506). It further checks the write flag for the internal address(11)b when the internal address is (10)b (S507) and verifies the memorycell with the internal address (11)b (S508). The address selected fromthe internal address storage 10 thereby reaches the last address, whichis the internal address (11)b in this case, and the first or the secondverify operation completes therewith. The first write operation isperformed in the same way as described above by selecting the internaladdresses (00)b to (11)b and writing the data to each address.

FIG. 8B shows the third verify operation in which the internal addressesand the write flags are in the states as shown in FIG. 4B.

Since it is initial condition, the next address calculator 8 checks allthe write flags for the internal addresses (00)b to (11)b at the sametime and calculates a minimum internal address for which the write flagis set (S509). Since the write flag for the internal address (00)b is(1)b, the internal address (00)b is calculated and set to the internaladdress storage 10 so that the internal address (00)b is selected. Then,the verify operation is performed on the memory cell with the internaladdress (00)b (S510).

Then, since the internal address (00)b is selected in the internaladdress storage 10, the next address calculator 8 checks all the writeflags for the address larger than (00)b, which is the internal addresses(01)b to (11)b, at the same time and calculates a minimum internaladdress for which the write flag is set (S511). Since the write flagsfor the internal addresses (01)b and (10)b are (0)b and the write flagfor the internal address (11)b is (1)b, the internal address (11)b iscalculated and set to the internal address storage 10 so that theinternal address (11)b is selected. Then, the verify operation isperformed on the memory cell with the internal address (11)b (S512).Then, the address selected by the internal address storage 10 reachesthe last address, which is the internal address (11)b in this case, andthereby the third verify operation completes. The second write operationis performed in the same way as described above by selecting theinternal addresses (00)b to (11)b and writing the data to each address.

As described in the foregoing, this embodiment selects only the addressfor which the write flag is set. This avoids selecting the addressesalways sequentially as in the first embodiment shown in FIG. 5, therebyreducing a processing time for the write flag search operation.

The structure and the operation of the next address calculator 8 aredescribed hereinafter. FIG. 9 shows the structure of the next addresscalculator 8. As shown in FIG. 9, the next address calculator 8 includesa next execution address calculator 81 and a last address calculator 82.

The next execution address calculator 81 inputs the current internaladdress and write flag and an initial set flag, calculates the nextaddress to be selected for which the write flag is set and outputs thecalculated address to the sequence controller 4. The next executionaddress calculator 81 serves as a next execution address selector whichchecks a plurality of flags stored in the flag information storage 3 atsubstantially the same time and selects the address of the set flag fromthe plurality of flags for each operation of data writing, erasing orverifying. The last address calculator 82 inputs the current internaladdress and write flag, calculates a last address flag which indicateswhether the internal address is a last address and outputs the result tothe sequence controller 4. The last address calculator 82 serves as alast address determinator which checks a plurality of flags stored inthe flag information storage 3 at substantially the same time uponselection of the address and, when all of the plurality of flags are notset, determines the completion of the data write, erase or verifyoperation.

In this example, the capacity of the buffer 1, which is the maximum sizeof written data, is 32 addresses. Thus, the number of write flags whichindicate that an address is a target for writing is 32, the internaladdress which is required for selecting the memory cell on which thedata is to be written is 5 bits (2⁵=32).

The current internal address, which is the internal address set to theinternal address storage 10, is referred to herein as ADD[4:0], whichrepresents 5 bits from 0th bit to 4th bit. The initial set flag which isgenerated by the sequence controller 4 and indicates the first addressselection operation is referred to as INITFLAG. The write flag which isstored in the flag information storage 3 and indicates a write target isreferred to as FLAG[31:0]. The next address which is the calculationresult of the next execution address calculator 81 is referred to asNEXT_ADD[4:0]. The last address flag which is the calculation result ofthe last address calculator 82 is referred to as LASTFLAG.

In this embodiment, the last address is not the final address where thecounter overflows as in the first embodiment, such as (1_(—)1111)b=(31)dif 5 bits. The last address in this embodiment is the final address ofthe addresses for which a write flag is set (addresses to which data isto be written) in the buffer 1. Thus, the last address does not meanthat it is always (1_(—)1111)b.

Referring then to the flowchart of FIG. 10, the address selectionoperation in the nonvolatile semiconductor memory according to thisembodiment is described hereinafter. FIG. 10 is the flowchart whichextracts the address selection operation from the flowchart of FIG. 7.

As initial setting, the sequence controller 4 resets the internaladdresses in the internal address storage 10(ADD[4:0]=(0_(—)0000)b=(0)d) and sets an initial set flag (INITFLAG=1)(S601).

Then, the next execution address calculator 81 calculates the nextaddress NEXT_ADD[4:0] (S602). At the same time, the last addresscalculator 82 calculates the last address flag LASTFLAG (S603). Thecalculation method in the next execution address calculator 81 and thelast address calculator 82 is detailed later.

After that, the sequence controller 4 sets the next addressNEXT_ADD[4:0] which is the calculation result of the next executionaddress calculator 81 to the internal address storage 10(ADD[4:0]=NEXT_ADD[4:0]) (S604). The memory cell corresponding to theaddress of the calculation result is thereby selected.

Then, the sequence controller 4 resets the initial set flag (INITFLAG=0)for the subsequent address calculation (S605).

The sequence controller 4 then determines whether the current internaladdress is a last address (LASTFLAG=1) by the last address flag which isthe calculation result of the last address calculator 82 (S606). If thelast address flag is not set (LASTFLAG=0), it means that the memory cellto be processed next exists. Thus, the next execution address calculator81 again calculates the address to be selected (S602). If, on the otherhand, the last address flag is set (LASTFLAG=1), it means that thecurrent internal address is the final address to be processed in thebuffer, and thereby the address selection operation completes.

The flowchart of FIG. 10 shows one-time address selection operation inthe buffer. The address selection operation in the buffer (operation ofFIG. 10) is performed a plurality of times in the flowchart of theautomatic write operation shown in FIG. 7 (S403 to S408, S410 to S413).

Referring now to the flowchart of FIG. 11, the method for calculatingthe next address NEXT_ADD[4:0] in the next execution address calculator81 is described hereinafter. The next execution address calculator 81compares the current internal address ADD[4:0] with the state of thewrite flag FLAG[31:0] and calculates the next address NEXT_ADD[4:0] tobe executed next.

The symbol “==” in FIG. 11 represents match determination, “<”represents magnitude relation determination, “&&” represents logicalproduct, and “<=” represents substitution. The following descriptionuses the symbol “=” as an equal sign.

The next execution address calculator 81 first determines whether thecurrent internal address is a top address (ADD[4:0]=(0)d), the writeflag for the top address is set (FLAG[0]=1) and further the initial setflag is set (INITFLAG=1) (S701). Thus, it determines whether the topaddress is a write target in the first address calculation. If theconditions of S701 are satisfied, the next execution address calculator81 sets the next address to the top address (NEXT_ADD[4:0]<=(0)d)(S707).

The reason that the condition of the initial set flag INITFLAG isrequired in S701 is because it is necessary to distinguish between thecase where the selected address is the top address in the first time,which is where the current internal address is ADD[4:0]=(0)d in thesecond address calculation also and the case where the current internaladdress is ADD[4:0]=(0)d in the first address calculation.

Further, the determination of the steps S702 to S706 is performed atsubstantially the same time as the step S701. The steps S702 to S706determine whether the write flag is set for the address next to thecurrent internal address including the address for which the flag is notset.

In S702, the next execution address calculator 81 determines whether thecurrent internal address is ADD[4:0]<(1)d, which is the top address(ADD[4:0]=(0)d), and the write flag for the 1st address is set(FLAG[Expression 14:1]=1). Since the determination of S701 is performedin preference to the determination of S702, the conditions in S702include that the conditions for S701 are not satisfied. If theconditions for S702 are satisfied, the next address is set to the 1staddress (NEXT_ADD[4:0]<=(1)d) (S708).

In S703, the next execution address calculator 81 determines whether thecurrent internal address is ADD[4:0]<(2)d, which is the top address(ADD[4:0]=(0)d) or 1st address (ADD[4:0]<=(1)d), and the write flag forthe 2nd address is set (FLAG[2]=1). Since the determination of S701 andS702 is performed in preference to the determination of S703, theconditions in S703 include that the conditions for S701 and S702 are notsatisfied. If the conditions for S703 are satisfied, the next address isset to the 2nd address (NEXT_ADD[4:0]<=(2)d) (S709).

Similarly, the next execution address calculator 81 performs thedetermination on the cases where the current internal address isADD[4:0]<(3)d to (30)d (S704, S705) and sets the next address(NEXT_ADD[4:0]<=(3)d to (30)d).

In S706, the next execution address calculator 81 determines whether thecurrent internal address is ADD[4:0]<(31)d, which is the top address tothe 30th address (ADD[4:0]=(0)d to (30)d), and the write flag for the31st address is set (FLAG[31]=1). If the conditions of S706 aresatisfied, the next address is set to the 31st address(NEXT_ADD[4:0]<=(31)d) (S712). If, on the other hand, the conditions ofS706 are not satisfied, the next address is set to the top address(NEXT_ADD[4:0]<=(0)d) (S713). Thus, the next address is reset in thiscase. However, since the last address calculator 82 determines theaddress to be the last address and terminates the process before thiscondition is satisfied, it is generally not selected.

In this way, this embodiment selects only the necessary address forwhich the write flag is set, thereby preventing the selection ofunnecessary addresses. In some cases, the selection may be made byjumping the addresses.

Referring then to the flowchart of FIG. 12, the method for calculatingthe last address flag LASTFLAG in the last address calculator 82 isdescribed hereinafter. The last address calculator 82 compares thecurrent internal address ADD[4:0] with the state of the write flagFLAG[31:0] and calculates whether the selected internal address is thelast address or not. In FIG. 12, the symbol “^(˜)” represents logicinversion and “|” represents a bit logical sum.

The last address calculator 82 determines whether the current internaladdress is a top address (ADD[4:0]=(0)d) and the write flags are not setfor all the addresses from the 1st to 31st address (^(˜)(|FLAG[31:1]))(S801). Thus, it determines whether the flags are not set for all theaddress after the current internal address. If the conditions of S801are satisfied, it means that the current internal address is the lastaddress. Therefore, the last address calculator 82 sets the last addressflag (LASTFLAG=1) (S808).

Further, at substantially the same time as the determination of S802,the determination of S802 to S806 are performed. The steps S802 to S806determine whether the flags are not set for all the address after thecurrent internal address just like S801.

In S802, the last address calculator 82 determines whether the currentinternal address is the 1st address (ADD[4:0]=(1)d) and the write flagsare not set for all of the 2nd to 31st address (^(˜)(|FLAG[31:2]))(S802). If the conditions of S802 are satisfied, it means that thecurrent internal address is the last address as in S801. Therefore, thelast address calculator 82 sets the last address flag (LASTFLAG=1)(S808).

Similarly, the last address calculator 82 performs the comparation onthe cases where the current internal address is ADD[4:0]=(2)d to (30)d(S804, S805) and sets the last address flag (LASTFLAG=1) (S808).

Further, in S806, when the current internal address is the 31st address(ADD[4:0]=(31)d), the last address calculator 82 sets the last addressflag (LASTFLAG=1) in order to indicate that the internal address is thelast address without recourse to the write flag (S808). If theconditions of S806 are not satisfied, it means that the current internaladdress ADD[4:0] is not the last address. Therefore, the last addresscalculator 82 resets the last address flag (LASTFLAG=0) (S807).

By calculating the last address flag based on the flags set for theaddresses after the current addresses, it is possible to terminate theprocess upon reaching the last of the necessary address for which thewrite flag is set without counting up the internal address storage 10for all bits. This prevents the selection of necessary addresses.

Referring further to FIGS. 13 and 14, detailed circuit configurations ofthe next execution address calculator 81 and the last address calculator82 are described hereinafter.

FIG. 13 shows an example of the circuit configuration of the nextexecution address calculator 81. This examples inputs the currentinternal address ADD[1:0], the write flag FLAG[3:0] and the initial setflag INITFLAG and outputs the next address NEXT_ADD[1:0].

As shown in FIG. 13, the next execution address calculator 81 iscomposed of a combinational circuit having logic gates denoted by 101 to118, which includes an inverter, an AND gate, a NAND gate, an OR gate, aNOR gate and a buffer.

The initial set flag INITFLAG is inverted and input to one inputterminal of the NAND gate 102. The write flag FLAG[0] is input to theother input terminal of the NAND gate 102. The write flag FLAG[1] isinput to the input terminal of the inverter 103. The write flag FLAG[2]is input to the input terminal of the inverter 101. The write flagFLAG[3] is input to the input terminal of the inverter 105. The currentaddress ADD[0] is input to the input terminal of the buffer 104. Thecurrent address ADD[1] is input to the input terminal of the buffer 106.

The outputs of the inverter 101, the NAND gate 102, the inverter 103,the buffer 104, the inverter 105 and the buffer 106 are input to thebuffer 116 through the AND gate 107, the NOR gate 108, the OR gate 109,the AND gate 110, the AND gate 111 and the NOR gate 112. The output ofthe buffer 116 is the next address NEXT_ADD[1]. Further, the outputs ofthe inverter 101, the NAND gate 102, the inverter 103, the buffer 104,the inverter 105 and the buffer 106 are input to the NOR gate 118through the AND gate 107, the NOR gate 108, the OR gate 109, the ANDgate 110, the AND gate 111, the NOR gate 112, and further through theAND gate 113, the NOR gate 114, the NAND gate 115 and the AND gate 117.The output of the NOR gate 118 is the next address NEXT_ADD[0].

The following Table 1 is a truth table that indicates the inputs and theoutputs in the next execution address calculator 81 shown in FIG. 13.

TABLE 1 INPUT CURRENT INITIAL OUTPUT ADDRESS WRITE FLAG SET FLAG NEXTADDRESS (00)b [0]==(1)b (1)b (00)b (00)b [1]==(1)b (0)b (01)b (00)b[1]==(0)b (0)b (10)b && [2]==(1)b (00)b [1]==(0)b (0)b (11)b &&[2]==(0)b && [3]==(1)b (01)b [2]==(1)b (0)b (10)b (01)b [2]==(0)b (0)b(11)b && [3]==(1)b (10)b [3]==(1)b (0)b (11)b (11)b — (0)b (11)b

Table 1 shows the same operation as in the flowchart of FIG. 11. Forexample, when the input is the current internal address ADD[1:0]=(00)b,the write flag FLAG[0]=1 and the initial set flag INITFLAG=1, the nextexecution address calculator 81 outputs the next addressNEXT_ADD[1:0]=(00)b.

When the input is the current internal address ADD[1:0]=(00)b, the writeflag FLAG[1]=0, the write flag FLAG[2]=0, the write flag FLAG[3]=1 andthe initial set flag INITFLAG=0, the next execution address calculator81 outputs the next address NEXT_ADD[1:0]=(11)b. At this time, itselects the internal address (11)b, not selecting the internal address(01)b or (10)b.

When the input is the current internal address ADD[1:0]=(01)b, the writeflag FLAG[2]=0, the write flag FLAG[3]=1 and the initial set flagINITFLAG=0, the next execution address calculator 81 outputs the nextaddress NEXT_ADD[1:0]=(11)b. At this time, it selects the internaladdress (11)b, not selecting the internal address (10)b.

The circuit of FIG. 13 may be composed of another combinational circuitas long as it operates as shown in Table 1.

FIG. 14 shows an example of the circuit configuration of the lastaddress calculator 82. This examples inputs the current internal addressADD[1:0], the write flag FLAG[3:0] and outputs the last address flagLASTFLAG.

As shown in FIG. 14, the last address calculator 82 is composed of acombinational circuit having logic gates denoted by 201 to 209, whichincludes an inverter, an AND gate, a NAND gate, an OR gate, and a NORgate.

The write flag FLAG[0] is not input since the last address calculator 82does not use it. The write flag FLAG[1] is inverted and input to oneinput terminal of the AND gate 203. The write flag FLAG[2] is input toone input terminal of the NOR gate 204. The write flag FLAG[3] is inputto the input terminal of the OR gate 207. The current address ADD[0] isinput to the input terminal of the inverter 201. The current addressADD[1] is input to the input terminal of the inverter 202.

The inputs are input to the NAND gate 209 through the inverter 201, theinverter 202, the AND gate 203, the NOR gate 204, the inverter 205, theNOR gate 206, the OR gate 207 and the OR gate 208. The output of theNAND gate 209 is the last address flag LASTFLAG.

The following Table 2 is a truth table that indicates the inputs and theoutputs in the last address calculator 82 shown in FIG. 14.

TABLE 2 INPUT OUTPUT CURRENT ADDRESS WRITE FLAG LAST ADDRESS FLAG (00)b[1]==(0)b (1)b && [2]==(0)b && [3]==(0)b (00)b [1]==(1)b (0)b ||[2]==(1)b || [3]==(1)b (01)b [2]==(0)b (1)b && [3]==(0)b (01)b [2]==(1)b(0)b || [3]==(1)b (10)b [3]==(0)b (1)b (10)b [3]==(1)b (0)b (11)b — (1)b

Table 2 shows the same operation as in the flowchart of FIG. 12. Forexample, when the input is the current internal address ADD[1:0]=(00)b,the write flag FLAG[1]=0, the write flag FLAG[2]=0 and the write flagFLAG[3]=0, the last address calculator 82 outputs the last address flagLASTFLAG=1. At this time, it selects the internal address (00)b as thelast address, not selecting the internal address (01)b, (10)b or (11)b.

When the input is the current internal address ADD[1:0]=(01)b, the writeflag FLAG[2]=0 and the write flag FLAG[3]=0, the last address calculator82 outputs the last address flag LASTFLAG=1. At this time, it selectsthe internal address (01)b as the last address, not selecting theinternal address (10)b or (11)b.

When the input is the current internal address ADD[1:0]=(10)b and thewrite flag FLAG[3]=0, the last address calculator 82 outputs the lastaddress flag LASTFLAG=1. At this time, it selects the internal address(10)b as the last address, not selecting the internal address (11)b.

The circuit of FIG. 14 may be composed of another combinational circuitas long as it operates as shown in Table 2.

A calculation example of an automatic write operation time according tothe first and the second embodiment is described hereinafter. Thecalculation is made under the condition where the number of writeaddresses in the buffer is 32 bits for the cases where the memory cellof the flash memory is multivalued and where it is binary. In the caseof using the multivalued flash memory, the write operation ends in 30times of writing and an electrical write pulse width is 500 ns. In thecase of using the binary flash memory, the write operation ends in onetime of writing and an electrical write pulse width is 2 us.

In this example, the automatic writing time is calculated in thesequence operation expressed by the following expressions. Expressions 1to 3 below respectively represents a processing time for pre-verify,program (writing) and post-verify according to the first embodiment.

PreVerify=search(50 ns)*number of all addresses+Verify(200 ns)*number ofnecessary addresses   Expression 1:

Program=search(50 ns)*number of all addresses+Program(XXns)*number ofnecessary addresses   Expression 2:

PostVerify=search(50 ns)*number of all addresses+Verify(200 ns)*numberof necessary addresses.   Expression 3:

Expressions 4 to 6 below respectively represents a processing time forpre-verify, program (writing) and post-verify according to the secondembodiment.

PreVerify=search(50 ns)*number of necessary addresses+Verify(200ns)*number of necessary addresses   Expression 4:

Program=search (50 ns)*number of necessaryaddresses+Program(XXns)*number of necessary addresses   Expression 5:

PostVerify=search(50 ns)*number of necessary addresses+Verify(200ns)*number of necessary addresses.   Expression 6:

Table 3 below shows the result of calculating a processing time in abinary flash memory according to the above expressions when the numberof write data segments is 4 to 32.

TABLE 3 TIME REDUCTION EFFECT FIRST EMBODIMENT SECOND EMBODIMENT SECONDNUMBER OF VERIFY/ VERIFY/ EMBODIMENT/ WRITE DATA SEARCH PROGRAM SEARCHPROGRAM FIRST SEGMENTS TIME TIME TOTAL TIME TIME TOTAL EMBODIMENT 324,800 76,800 81,600 4,800 76,800 81,600 0 100.0% 16 4,800 38,400 43,2002,400 38,400 40,800 −2,400 94.4% 8 4,800 19,200 24,000 1,200 19,20020,400 −3,600 85.0% 4 4,800 9,600 14,400 600 9,600 10,200 −4,200 70.8%

As shown in Table 3, if the number of write data segments is 32, thedata segments are stored entirely in the buffer 1 and therefore there isno difference in search time. Thus, a processing time is the samebetween the first embodiment and the second embodiment. Since a searchtime in the second embodiment decreases as the number of write datasegments decreases, the overall processing time decreases accordingly.If the number of write data segments is 4, a processing time in thesecond embodiment is 70.8% of a processing time in the first embodiment.

Table 4 below shows the result of calculating a processing time in amultivalued flash memory according to the above expressions when thenumber of write data segments is 4 to 32.

TABLE 4 TIME REDUCTION EFFECT FIRST EMBODIMENT SECOND EMBODIMENT SECONDNUMBER OF VERIFY/ VERIFY/ EMBODIMENT/ WRITE DATA SEARCH PROGRAM SEARCHPROGRAM FIRST SEGMENTS TIME TIME TOTAL TIME TIME TOTAL EMBODIMENT 3297,600 678,400 776,000 97,600 678,400 776,000 0 100.0% 16 97,600 339,200436,800 48,800 339,200 388,000 −48,800 88.8% 8 97,600 169,600 267,20024,400 169,600 194,000 −73,200 72.6% 4 97,600 84,800 182,400 12,20084,800 97,000 −85,400 53.2%

FIG. 15 shows the graph of the time reduction effect in Tables 3 and 4.As shown in Tables 3 and 4 and FIG. 15, if the number of write datasegments is 32, the data segments are stored entirely in the buffer 1and therefore there is no difference in search time. Thus, a processingtime is the same between the first embodiment and the second embodiment,and no time reduction effect is obtained. As the number of write datasegments decreases, since the second embodiment can eliminate theunnecessary address selection process to reduce a search time, theoverall processing time decreases accordingly, thus increasing the timereduction effect. For example, in the case of the binary flash memory,if the number of write data segments is 4, the processing time in thefirst embodiment is 14.4 us while the processing time in the secondembodiment is 10.2 us, such that the processing time in the secondembodiment is 70.8% of the processing time in the first embodiment.

Since the number of retrying the electrical writing and the number ofaddresses for which the writing is unnecessary is larger in themultivalued flash memory than in the binary flash memory, the effect ofincreasing the processing speed is more significant in the multivaluedflash memory.

For example, if the calculation formula is expressed for the case wherethe number of write data segments is 4 when using the multivalued flashmemory, the processing time in the first embodiment may be representedby the following Expressions 7 to 10:

PreVerify=(50 ns*32addresses)+(200 ns*4addresses)=2.4 us   Expression 7:

Program=(50 ns*32addresses)+(500 ns*4addresses)=3.6 us   Expression 8:

PostVerify=(50 ns*32addresses)+(200 ns*4addresses)=2.4 us   Expression9:

Total=(Expression7)+(Expression8+Expression9)*30 =182.4 us.   Expression10:

The calculation result of the processing time in the second embodimentunder the same conditions is as represented by the following Expressions11 to 14:

PreVerify=(50 ns*4addresses)+(200 ns*4addresses)=1.0 us   Expression 11:

Program=(50 ns*4addresses)+(500 ns*4addresses)=2.2 us   Expression 12:

PostVerify=(50 ns*4addresses)+(200 ns*4addresses)=1.0 us   Expression13:

Total=(Expression11)+(Expression12+Expression13)*30 =97.0 us.  Expression 14:

Accordingly, the processing time in the first embodiment is 182.4 us andthe processing time in the second embodiment is 97.0 us. Thus, theprocessing time in the second embodiment is reduced to 53.2% of theprocessing time in the first embodiment.

As described in the foregoing, in the process of searching for theaddress to be verified or written, this embodiment does not sequentiallyselect all addresses as in the first embodiment but selects only theaddresses for which the write flag is set. This eliminates theunnecessary address selection operation and therefore reduces theprocessing time for the write operation, thus increasing the writeoperation speed.

Further, if a multivalued flash memory is used for the memory cell towhich data is to be written, the number of retrying times increases andthus the number of times of performing the address selection operationincreases accordingly, thus enabling a further increase in theprocessing speed.

Furthermore, if unnecessary voltage application occurs in the memorycell array when selecting an address, the use of this embodiment enablesthe prevention of the application of an unnecessary electrical stress.

Third Embodiment

The nonvolatile semiconductor memory according to the third embodimentof the present invention is described hereinafter. The nonvolatilesemiconductor memory of this embodiment is the same as that of thesecond embodiment except for the next address calculator 8. Thus, thestructure is not described in detail herein.

The second embodiment requires the comparison operation with arelatively large number of stages. For example, if the internal addressis 2 bits, the circuit configurations of the next execution addresscalculator 81 and the last address calculator 82 are as shown in FIGS.13 and 14. As the number of bits of the internal address increases, thecircuit configuration becomes more complicated. Thus, the comparisonoperation can be too late depending on the circuit operationspecification.

In order to overcome this drawback, the present embodiment divides theprocess of the next execution address calculator 81 shown in theflowchart of FIG. 11 and the process of the last address calculator 82shown in the flowchart of FIG. 12 included in the next addresscalculator 8 into a plurality of stages. Further, it provides a selectorin the final stage so as to select and output a necessary operationresult.

FIG. 16 is a block diagram showing the case of dividing the process intotwo stages, for example. In the next execution address calculator 81,the process is divided into a first next execution address calculator811 and a second next execution address calculator 812. For example, inthe flowchart of FIG. 11, the determination on the write flags FLAG[0]to FLAG[15] is implemented by the first next execution addresscalculator (first next execution address selector) 811 and thedetermination on the write flags FLAG[16] to FLAG[31] is implemented bythe second next execution address calculator (second next executionaddress selector) 812. Finally, a selector (first determinator) 813selects either one of the address calculated by the first next executionaddress calculator 811 or the address calculated by the second nextexecution address calculator 812 and outputs the result.

Similarly, in the last address calculator 82, the process is dividedinto a first last address calculator 821 and a second last addresscalculator 822. The determination on the current internal address ADD[b4:0]=(0)d to (15)d in the flowchart of FIG. 12 is implemented in thefirst last address calculator (first last address determinator) 821 andthe determination on the current internal address ADD[4:0]=(16)d to(315)d is implemented in the second last address calculator (second lastaddress determinator) 822. Finally, a selector (second determinator) 823selects either one of the last address flag determined by the first lastaddress calculator 821 or the last address flag determined by the secondlast address calculator 822 and outputs the result.

As described in the foregoing, this embodiment divides the calculationprocessing of the next address calculator into a plurality of circuits,thereby further increasing the write operation speed. It is therebypossible to obtain a sufficiently high operation speed even when thenumber of addresses in the buffer increases or when the calculationprocessing time of the next address calculator does not satisfy thecircuit operation specification.

Other Embodiments

Although the address selection operation in the above-describedembodiments selects the address in the ascending order from the topaddress to the last address, it is not limited thereto. The operationmay select the address in the descending order, which has the sameeffects. Thus, the present invention may be applied to the case wherethe address should be selected in the descending order due to theconfiguration of the memory cell array, for example, without thereduction of the effects.

Further, through the data write operation to the memory cell is mainlydescribed in the above embodiments, it is not limited thereto and thepresent invention may be applied to the data erase operation. In thedata erase operation, the above-described address selection isimplemented in the write operation before erasing, the erase operation,the write-back operation and the read operation for each of theseoperations, and it is possible to reduce the erase operation time.

It is apparent that the present invention is not limited to the aboveembodiment that may be modified and changed without departing from thescope and spirit of the invention.

1. A semiconductor memory comprising: a nonvolatile memory cell array; abuffer receiving and storing a data block including a plurality of writedata; and a write circuit writing said plurality of write data into saidnonvolatile memory cell array in a first write operation and writing afailure data in a second write operation different from said first writeoperation, said failure data indicating that a data failed to be writteninto said memory cell array in said write operation.
 2. Thesemiconductor memory according to claim 1, further comprising; a flaginformation storage storing a plurality of write flags indicatingwhether writing each of said plurality of write data into saidnonvolatile memory cell array succeeded or not.
 3. The semiconductormemory according to claim 2, further comprising: a sequence controllersetting values of said write flags in response to said first writeoperation and said second write operation.
 4. The semiconductor memoryaccording to claim 3, further comprising: a comparator determiningwhether a data stored in said nonvolatile memory cell array and one ofsaid plurality of write data corresponding to said data stored in saidnonvolatile memory cell array are same or not, wherein said sequencecontroller sets said values of said write flags in accordance with adetermination of said comparator.
 5. The semiconductor memory accordingto claim 4, further comprising: a read circuit reading a data stored insaid nonvolatile memory cell array and outputting said read data to saidcomparator.
 6. The semiconductor memory according to claim 1, furthercomprising: an internal address counter storing an address of saidnonvolatile memory cell array, wherein one of said plurality of writedata corresponding to said address is written into said nonvolatilememory cell array, wherein said internal address counter increments avalue of said address in response to finishing writing said one of saidplurality of write data into said nonvolatile memory cell array.
 7. Thesemiconductor memory according to claim 6, further comprising: asequence controller that determines whether said address is a finaladdress to be counted or not.
 8. The semiconductor memory according toclaim 7, wherein said sequence controller determines that said addresscorresponds to said final address when said internal address counteroverflows.
 9. The semiconductor memory according to claim 1, furthercomprising: an internal address storage storing a current address foraccessing said nonvolatile memory cell array; and a next addresscalculator calculating a next address based on said current addressstored in said internal address storage, said next address being storedin said internal address storage for a next access.
 10. Thesemiconductor memory according to claim 9, wherein said next address islarger than said current address and the smallest among addressescorresponding to said failure data.
 11. The nonvolatile semiconductormemory according to claim 10, wherein said next address calculatorcalculates a final address to be stored in said internal addressstorage.